1. Field of the Invention
The present invention relates in general to fabrication of semiconductor devices and more particularly to a method for fabricating a substrate structure comprising an epitaxial layer of a compound semiconductor material grown heteroepitaxially on a semiconductor wafer.
2. Description of the Related Art
Semiconductor devices fabricated on the substrate of compound semiconductors such as gallium arsenide (GaAs) have excellent operational characteristics such as high operational speed because of the high electron mobility pertinent to the compound semiconductors. Thus, various integrated circuits are constructed using the compound semiconductor material as the substrate.
As the substrate of such a compound semiconductor integrated circuits, the use of a single crystal wafer of a compound semiconductor material such as GaAs is of course possible. However, the fabrication of a large diameter GaAs wafer is currently difficult and expensive, because of the difficulty in growing a GaAs ingot without substantial defects or dislocations therein, difficulty of handling a large diameter GaAs wafer due to the brittle nature of GaAs, and the like. Because of this, attempts are made to grow a thin substrate layer of single crystal GaAs heteroepitaxially on a wafer of silicon which can be fabricated by a well established process even when the diameter of the wafer is increased.
Using the currently available technique, the heteroepitaxial growth of GaAs on silicon itself can be made without difficulty. However, the process for growing a single crystal GaAs layer on silicon with a quality which is suitable for use as the substrate of the compound semiconductor devices or integrated circuits, is still not established and intensive efforts are made for growing a GaAs substrate layer on a silicon wafer with such a quality that the dislocation density of about 10.sup.6 cm.sup.-2 or less is achieved.
The reason why the dislocations are introduced into the GaAs substrate layer when it is grown on the silicon substrate heteroepitaxially, is attributed to the large difference in the lattice constant and the thermal expansion between these two materials. It should be noted that the lattice constant of GaAs is larger than that of silicon by about 4%. Thus, crystal lattices of the two materials cause a slip or discrepancy at the interface between the silicon wafer and the GaAs substrate layer, and these discrepancies are propagated towards the surface of the GaAs substrate layer as dislocations.
In order to prevent the propagation of the dislocations into the interior of the GaAs substrate layer, a process of cyclic annealing is proposed. According to this process, a GaAs substrate layer is grown heteroepitaxially on a silicon wafer at about 800.degree. C. at first, and the temperature at which the wafer and the substrate are held is increased and decreased repeatedly between 850.degree. C. and 550.degree. C. When such a cyclic process is applied, tensile stresses and compressive stresses appear alternately in the GaAs substrate layer, and the dislocations are moved within the GaAs substrate layer in response to the stresses thus induced. During the movement of the dislocations, there occurs a case wherein two dislocations meet each other. When such a meeting or intersection of the dislocations occurs, there is a chance that the discrepancy of the crystal lattice causing the dislocations are cancelled each other. Thereby, a closed loop of dislocation is formed in the GaAs substrate and further propagation of the dislocations in the GaAs substrate layer towards its top surface is prevented.
FIG.1A shows a typical heteroepitaxial substrate structure 10 for use as the substrate of the compound semiconductor material. The substrate structure comprises a silicon wafer 11 and a GaAs heteroepitaxial substrate layer 12 grown thereon. In this structure, there are formed a number of slips or discrepancy of the crystal lattice in correspondence to the interface between the silicon wafer 11 and the GaAs layer 12, and a number of dislocations 14 are nucleated from this interface. These dislocations 14 extend in the GaAs crystal forming the layer 12 along the [101] direction and can move freely either in the [011] or [011] direction within the (111) plane of the GaAs crystal. Some of the dislocations 14 extend throughout the GaAs layer 12 and reaches its top surface. It should be noted that the top surface of the GaAs heteroepitaxial substrate layer 12 is defined by the (100) surface and the dislocations move somewhat perpendicularly with respect to the sheet of FIG. 1A.
When the structure shown in FIG. 1A is subjected to a cyclic annealing process as described, it is thought that each of the dislocations is moved in one of the [011] and [011] directions, and when two dislocations meet each other during the movement, there arises a case wherein the discrepancy of the crystal lattice causing the dislocations is cancelled each other. Thereby a loop 14' of dislocation is formed at the interface such that the loop 14' extends into the substrate layer 12 and returns again to the interface as shown in FIG. 1B. When such a loop is formed, further propagation of the dislocations 14 toward the top surface of the heteroepitaxial substrate layer 12 is prevented and the dislocation density in the vicinity of the top surface of the heteroepitaxial substrate layer 12 is significantly reduced. The dislocations formed in the silicon wafer 11 are not important with respect to the object of the present invention and will not be considered any further.
In the actual semiconductor devices, another GaAs layer not illustrated is grown further on the heteroepitaxial GaAs layer 12 as the substrate layer for decreasing the dislocation density in the substrate layer further. In this case, the GaAs layer 12 acts as the buffer layer.
In such a prior art cyclic annealing process, however, the dislocation density cannot be reduced below 6-7.times.10.sup.6 cm.sup.-2 as shown in FIG. 2 even with the cyclic annealing repeated more than five times. Such a decrease of the dislocation density is unsatisfactory because a dislocation density of less than 10.sup.6 cm.sup.-2 is required for the substrate layer 12 when constructing a semiconductor device thereon.